July 2010The applications for Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR). Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high-performance, low-cost DSP solutions. In order to meet these requirements, the processing elements and their supporting hardware platforms must be able to provide increased calculation throughput without the cost of additional latency.
The LatticeECP3 FPGA features a dual slice architecture with the ability to cascade/chain DSP slices and an enhanced instruction set, making it a compelling solution for various digital signal processing applications including FIR filters and FFT/iFFT implementations.
The LatticeECP3 sysDSP slices are located in rows throughout the FPGA device. The figure below shows a simplified block diagram of two sysDSP slices, each of which includes multipliers, ALU, muxes, pipeline registers, a shift register chain and cascade chain. The ALU can be configured as an adder, subtractor, or accumulator.
LatticeECP3 sysDSP Block Diagram
Designers can graphically specify various high-performance modes including MULT (multiplier), MAC (multiplier accumulate), MMAC (multiplier multiplier accumulate), MULTADDSUB (multiplier add/subtract), MULTADDSUBSUM (multiply add/subtract and sum), Adder Tree, Wide Mux, Barrel Shifter, and Slice (for advanced functions).
A filter is a device or process that removes some unwanted component from a signal (typically to allow only some frequencies in a signal to pass). A Finite Impulse Response (FIR) filter is one of the most popular types of filters and is usually implemented by using a series of delays, multipliers, and adders to create the filter's output. The filter design is the process of selecting the filter's length and coefficients. The longer or more taps the filter has, the more finely the response can be tuned.
The FIR Filter Generator IP core is a widely configurable, multi-channel FIR filter, implemented using high-performance DSP available in Lattice devices. In addition to single-rate filters, the IP core also supports a range of polyphase decimation and interpolation filters. The utilization versus throughput trade-off can be controlled by specifying the number of multipliers used for implementing the filter. For example, using one multiplier results in the best resource utilization, whereas using as many multipliers as the number of taps results in the best throughput. The FIR Filter IP core supports as many as 256 channels, with each having up to 2,048 taps.
The following are some examples of long filter designs that can be created using the sysDSP blocks in the LatticeECP3 FPGA.
Direct Form 64-Tap FIR Filter: In the direct form FIR filter, the input samples are shifted into a shift register queue and each shift register is connected to a multiplier. The products from the multipliers are added together to get the FIR filter’s output sample. This example shows a 64-tap FIR filter using 16 sysDSP blocks and approximately 512 slices in the LatticeECP3 FPGA.
Typical FIR Filter Using LatticeECP3 DSP Slice in MULTADDSUB Mode
128-Tap Long Asymmetrical Filters Using Ladder Architecture: Using the ladder architecture, the FIR filter is split into sections each having the same coefficient set as if it was a single continuous filter chain. Instead of connecting the shifted data and the result outputs from the first section to the corresponding input of the next section, the ladder network connects a delayed version of the first stage input data to the second stage input data and sums a delayed version of the first stage sum output with the second stage sum output.
Implementing 128-Tap Long Asymmetrical Filters Using the LatticeECP3 Ladder Architecture
256-Tap Long Symmetrical Filters Using Ladder Architecture: The impulse response for most FIR filters is symmetric. This symmetry can generally be exploited to reduce the arithmetic requirements and produce area-efficient filter realizations. It is possible to use only half the multipliers for symmetric coefficients compared to that used for a similar filter with non-symmetric coefficients. An implementation for symmetric coefficients is shown in the figure below. The 256-tap long symmetrical filter example uses only 32 sysDSP slices, two EBR and 3.5K slices.
Implementing 256-Tap Long Symmetrical Filters using Ladder Architecture
Polyphase Interpolator FIR Filter Designs: The polyphase interpolation filter implements the computationally efficient 1-to-P interpolation filter where P is an integer greater than 1. The example below shows a design with an interpolation by 16 that uses 128 taps. This requires eight polyphase filters (sub-filters) with 16 coefficients each.
Polyphase Interpolator FIR Filter
Download the above reference designs to evaluate the powerful DSP capability of the LatticeECP3 FPGA.
© Lattice Semiconductor Corporation 2012
